A Review on Clock Gating Methodologies for power minimization in VLSI circuits

This research paper gives the introduction of the various clock gating techniques. It also provides the basic clock gating principles, benefits, limitations and enhancements in traditional clock gating scheme. Also it provides the details of parameters which can affect the implementation of the clock gating. As clock signal having great source of power consumption and this is a critical problem in every synchronous circuit. Clock gating is an effective way of reducing the dynamic power dissipation in digital circuits. In a typical synchronous circuit such as the general purpose microprocessor, only a portion of the circuit is active at any given time. Hence, by shutting down the idle portion of the circuit, the unnecessary power consumption can be prevented. One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This project we will review existing clock gating approaches and also make a comparative analysis of those clock gating technique on some synchronous digital design like ALU (Arithmetic logical unit) and FIFO(first in first out) etc.